/********************************************************************/
/* Coldfire C Header File
 *
 *     Date      : 2009/04/30
 *     Revision  : 0.8
 *
 *     Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 *     http      : www.freescale.com
 *     mail      : support@freescale.com
 */

#ifndef __MCF52259_PWM_H__
#define __MCF52259_PWM_H__


/*********************************************************************
*
* Pulse Width Modulation (PWM)
*
*********************************************************************/

/* Register read/write macros */
#define MCF_PWM_PWME                         (*(vuint8 *)(0x401B0000))
#define MCF_PWM_PWMPOL                       (*(vuint8 *)(0x401B0001))
#define MCF_PWM_PWMCLK                       (*(vuint8 *)(0x401B0002))
#define MCF_PWM_PWMPRCLK                     (*(vuint8 *)(0x401B0003))
#define MCF_PWM_PWMCAE                       (*(vuint8 *)(0x401B0004))
#define MCF_PWM_PWMCTL                       (*(vuint8 *)(0x401B0005))
#define MCF_PWM_PWMSCLA                      (*(vuint8 *)(0x401B0008))
#define MCF_PWM_PWMSCLB                      (*(vuint8 *)(0x401B0009))
#define MCF_PWM_PWMCNT0                      (*(vuint8 *)(0x401B000C))
#define MCF_PWM_PWMCNT1                      (*(vuint8 *)(0x401B000D))
#define MCF_PWM_PWMCNT2                      (*(vuint8 *)(0x401B000E))
#define MCF_PWM_PWMCNT3                      (*(vuint8 *)(0x401B000F))
#define MCF_PWM_PWMCNT4                      (*(vuint8 *)(0x401B0010))
#define MCF_PWM_PWMCNT5                      (*(vuint8 *)(0x401B0011))
#define MCF_PWM_PWMCNT6                      (*(vuint8 *)(0x401B0012))
#define MCF_PWM_PWMCNT7                      (*(vuint8 *)(0x401B0013))
#define MCF_PWM_PWMPER0                      (*(vuint8 *)(0x401B0014))
#define MCF_PWM_PWMPER1                      (*(vuint8 *)(0x401B0015))
#define MCF_PWM_PWMPER2                      (*(vuint8 *)(0x401B0016))
#define MCF_PWM_PWMPER3                      (*(vuint8 *)(0x401B0017))
#define MCF_PWM_PWMPER4                      (*(vuint8 *)(0x401B0018))
#define MCF_PWM_PWMPER5                      (*(vuint8 *)(0x401B0019))
#define MCF_PWM_PWMPER6                      (*(vuint8 *)(0x401B001A))
#define MCF_PWM_PWMPER7                      (*(vuint8 *)(0x401B001B))
#define MCF_PWM_PWMDTY0                      (*(vuint8 *)(0x401B001C))
#define MCF_PWM_PWMDTY1                      (*(vuint8 *)(0x401B001D))
#define MCF_PWM_PWMDTY2                      (*(vuint8 *)(0x401B001E))
#define MCF_PWM_PWMDTY3                      (*(vuint8 *)(0x401B001F))
#define MCF_PWM_PWMDTY4                      (*(vuint8 *)(0x401B0020))
#define MCF_PWM_PWMDTY5                      (*(vuint8 *)(0x401B0021))
#define MCF_PWM_PWMDTY6                      (*(vuint8 *)(0x401B0022))
#define MCF_PWM_PWMDTY7                      (*(vuint8 *)(0x401B0023))
#define MCF_PWM_PWMSDN                       (*(vuint8 *)(0x401B0024))
#define MCF_PWM_PWMCNT(x)                    (*(vuint8 *)(0x401B000C + ((x)*0x1)))
#define MCF_PWM_PWMPER(x)                    (*(vuint8 *)(0x401B0014 + ((x)*0x1)))
#define MCF_PWM_PWMDTY(x)                    (*(vuint8 *)(0x401B001C + ((x)*0x1)))


/* Bit definitions and macros for MCF_PWM_PWME */
#define MCF_PWM_PWME_PWME0                   (0x1)
#define MCF_PWM_PWME_PWME1                   (0x2)
#define MCF_PWM_PWME_PWME2                   (0x4)
#define MCF_PWM_PWME_PWME3                   (0x8)
#define MCF_PWM_PWME_PWME4                   (0x10)
#define MCF_PWM_PWME_PWME5                   (0x20)
#define MCF_PWM_PWME_PWME6                   (0x40)
#define MCF_PWM_PWME_PWME7                   (0x80)

/* Bit definitions and macros for MCF_PWM_PWMPOL */
#define MCF_PWM_PWMPOL_PPOL0                 (0x1)
#define MCF_PWM_PWMPOL_PPOL1                 (0x2)
#define MCF_PWM_PWMPOL_PPOL2                 (0x4)
#define MCF_PWM_PWMPOL_PPOL3                 (0x8)
#define MCF_PWM_PWMPOL_PPOL4                 (0x10)
#define MCF_PWM_PWMPOL_PPOL5                 (0x20)
#define MCF_PWM_PWMPOL_PPOL6                 (0x40)
#define MCF_PWM_PWMPOL_PPOL7                 (0x80)

/* Bit definitions and macros for MCF_PWM_PWMCLK */
#define MCF_PWM_PWMCLK_PCLK0                 (0x1)
#define MCF_PWM_PWMCLK_PCLK1                 (0x2)
#define MCF_PWM_PWMCLK_PCLK2                 (0x4)
#define MCF_PWM_PWMCLK_PCLK3                 (0x8)
#define MCF_PWM_PWMCLK_PCLK4                 (0x10)
#define MCF_PWM_PWMCLK_PCLK5                 (0x20)
#define MCF_PWM_PWMCLK_PCLK6                 (0x40)
#define MCF_PWM_PWMCLK_PCLK7                 (0x80)

/* Bit definitions and macros for MCF_PWM_PWMPRCLK */
#define MCF_PWM_PWMPRCLK_PCKA(x)             (((x)&0x7)<<0)
#define MCF_PWM_PWMPRCLK_PCKB(x)             (((x)&0x7)<<0x4)

/* Bit definitions and macros for MCF_PWM_PWMCAE */
#define MCF_PWM_PWMCAE_CAE0                  (0x1)
#define MCF_PWM_PWMCAE_CAE1                  (0x2)
#define MCF_PWM_PWMCAE_CAE2                  (0x4)
#define MCF_PWM_PWMCAE_CAE3                  (0x8)
#define MCF_PWM_PWMCAE_CAE4                  (0x10)
#define MCF_PWM_PWMCAE_CAE5                  (0x20)
#define MCF_PWM_PWMCAE_CAE6                  (0x40)
#define MCF_PWM_PWMCAE_CAE7                  (0x80)

/* Bit definitions and macros for MCF_PWM_PWMCTL */
#define MCF_PWM_PWMCTL_PFRZ                  (0x4)
#define MCF_PWM_PWMCTL_PSWAI                 (0x8)
#define MCF_PWM_PWMCTL_CON01                 (0x10)
#define MCF_PWM_PWMCTL_CON23                 (0x20)
#define MCF_PWM_PWMCTL_CON45                 (0x40)
#define MCF_PWM_PWMCTL_CON67                 (0x80)

/* Bit definitions and macros for MCF_PWM_PWMSCLA */
#define MCF_PWM_PWMSCLA_SCALEA(x)            (((x)&0xFF)<<0)

/* Bit definitions and macros for MCF_PWM_PWMSCLB */
#define MCF_PWM_PWMSCLB_SCALEB(x)            (((x)&0xFF)<<0)

/* Bit definitions and macros for MCF_PWM_PWMCNT */
#define MCF_PWM_PWMCNT_COUNT(x)              (((x)&0xFF)<<0)

/* Bit definitions and macros for MCF_PWM_PWMPER */
#define MCF_PWM_PWMPER_PERIOD(x)             (((x)&0xFF)<<0)

/* Bit definitions and macros for MCF_PWM_PWMDTY */
#define MCF_PWM_PWMDTY_DUTY(x)               (((x)&0xFF)<<0)

/* Bit definitions and macros for MCF_PWM_PWMSDN */
#define MCF_PWM_PWMSDN_SDNEN                 (0x1)
#define MCF_PWM_PWMSDN_PWM7IL                (0x2)
#define MCF_PWM_PWMSDN_PWM7IN                (0x4)
#define MCF_PWM_PWMSDN_LVL                   (0x10)
#define MCF_PWM_PWMSDN_RESTART               (0x20)
#define MCF_PWM_PWMSDN_IE                    (0x40)
#define MCF_PWM_PWMSDN_IF                    (0x80)


/*** PWMPER01 - PWM Channel Period 01 Register; 0x001B0014 ***/
#define PWMPER01                      (*((volatile uint16 *)(&__IPSBAR[0x001B0014UL])))
#define PWMPER01_BIT0_BITMASK         (0x1U)
#define PWMPER01_BIT1_BITMASK         (0x2U)
#define PWMPER01_BIT2_BITMASK         (0x4U)
#define PWMPER01_BIT3_BITMASK         (0x8U)
#define PWMPER01_BIT4_BITMASK         (0x10U)
#define PWMPER01_BIT5_BITMASK         (0x20U)
#define PWMPER01_BIT6_BITMASK         (0x40U)
#define PWMPER01_BIT7_BITMASK         (0x80U)
#define PWMPER01_BIT8_BITMASK         (0x100U)
#define PWMPER01_BIT9_BITMASK         (0x200U)
#define PWMPER01_BIT10_BITMASK        (0x400U)
#define PWMPER01_BIT11_BITMASK        (0x800U)
#define PWMPER01_BIT12_BITMASK        (0x1000U)
#define PWMPER01_BIT13_BITMASK        (0x2000U)
#define PWMPER01_BIT14_BITMASK        (0x4000U)
#define PWMPER01_BIT15_BITMASK        (0x8000U)

/*** PWMPER0 - PWM Channel 0 Period Register.; 0x001B0014 ***/
#define PWMPER0                       (*((volatile uint8 *)(&__IPSBAR[0x001B0014UL])))
#define PWMPER0_PERIOD0_BITMASK       (0x1U)
#define PWMPER0_PERIOD1_BITMASK       (0x2U)
#define PWMPER0_PERIOD2_BITMASK       (0x4U)
#define PWMPER0_PERIOD3_BITMASK       (0x8U)
#define PWMPER0_PERIOD4_BITMASK       (0x10U)
#define PWMPER0_PERIOD5_BITMASK       (0x20U)
#define PWMPER0_PERIOD6_BITMASK       (0x40U)
#define PWMPER0_PERIOD7_BITMASK       (0x80U)
#define PWMPER0_PERIOD_GRPMASK        (0xFFU)
#define PWMPER0_PERIOD_GRPPOS         (0U)

/*** PWMPER1 - PWM Channel 1 Period Register.; 0x001B0015 ***/
#define PWMPER1                       (*((volatile uint8 *)(&__IPSBAR[0x001B0015UL])))
#define PWMPER1_PERIOD0_BITMASK       (0x1U)
#define PWMPER1_PERIOD1_BITMASK       (0x2U)
#define PWMPER1_PERIOD2_BITMASK       (0x4U)
#define PWMPER1_PERIOD3_BITMASK       (0x8U)
#define PWMPER1_PERIOD4_BITMASK       (0x10U)
#define PWMPER1_PERIOD5_BITMASK       (0x20U)
#define PWMPER1_PERIOD6_BITMASK       (0x40U)
#define PWMPER1_PERIOD7_BITMASK       (0x80U)
#define PWMPER1_PERIOD_GRPMASK        (0xFFU)
#define PWMPER1_PERIOD_GRPPOS         (0U)

/*** PWMPER23 - PWM Channel Period 23 Register; 0x001B0016 ***/
#define PWMPER23                      (*((volatile uint16 *)(&__IPSBAR[0x001B0016UL])))
#define PWMPER23_BIT0_BITMASK         (0x1U)
#define PWMPER23_BIT1_BITMASK         (0x2U)
#define PWMPER23_BIT2_BITMASK         (0x4U)
#define PWMPER23_BIT3_BITMASK         (0x8U)
#define PWMPER23_BIT4_BITMASK         (0x10U)
#define PWMPER23_BIT5_BITMASK         (0x20U)
#define PWMPER23_BIT6_BITMASK         (0x40U)
#define PWMPER23_BIT7_BITMASK         (0x80U)
#define PWMPER23_BIT8_BITMASK         (0x100U)
#define PWMPER23_BIT9_BITMASK         (0x200U)
#define PWMPER23_BIT10_BITMASK        (0x400U)
#define PWMPER23_BIT11_BITMASK        (0x800U)
#define PWMPER23_BIT12_BITMASK        (0x1000U)
#define PWMPER23_BIT13_BITMASK        (0x2000U)
#define PWMPER23_BIT14_BITMASK        (0x4000U)
#define PWMPER23_BIT15_BITMASK        (0x8000U)

/*** PWMPER2 - PWM Channel 2 Period Register.; 0x001B0016 ***/
#define PWMPER2                       (*((volatile uint8 *)(&__IPSBAR[0x001B0016UL])))
#define PWMPER2_PERIOD0_BITMASK       (0x1U)
#define PWMPER2_PERIOD1_BITMASK       (0x2U)
#define PWMPER2_PERIOD2_BITMASK       (0x4U)
#define PWMPER2_PERIOD3_BITMASK       (0x8U)
#define PWMPER2_PERIOD4_BITMASK       (0x10U)
#define PWMPER2_PERIOD5_BITMASK       (0x20U)
#define PWMPER2_PERIOD6_BITMASK       (0x40U)
#define PWMPER2_PERIOD7_BITMASK       (0x80U)
#define PWMPER2_PERIOD_GRPMASK        (0xFFU)
#define PWMPER2_PERIOD_GRPPOS         (0U)

/*** PWMPER3 - PWM Channel 3 Period Register.; 0x001B0017 ***/
#define PWMPER3                       (*((volatile uint8 *)(&__IPSBAR[0x001B0017UL])))
#define PWMPER3_PERIOD0_BITMASK       (0x1U)
#define PWMPER3_PERIOD1_BITMASK       (0x2U)
#define PWMPER3_PERIOD2_BITMASK       (0x4U)
#define PWMPER3_PERIOD3_BITMASK       (0x8U)
#define PWMPER3_PERIOD4_BITMASK       (0x10U)
#define PWMPER3_PERIOD5_BITMASK       (0x20U)
#define PWMPER3_PERIOD6_BITMASK       (0x40U)
#define PWMPER3_PERIOD7_BITMASK       (0x80U)
#define PWMPER3_PERIOD_GRPMASK        (0xFFU)
#define PWMPER3_PERIOD_GRPPOS         (0U)

/*** PWMPER45 - PWM Channel Period 45 Register; 0x001B0018 ***/
#define PWMPER45                      (*((volatile uint16 *)(&__IPSBAR[0x001B0018UL])))
#define PWMPER45_BIT0_BITMASK         (0x1U)
#define PWMPER45_BIT1_BITMASK         (0x2U)
#define PWMPER45_BIT2_BITMASK         (0x4U)
#define PWMPER45_BIT3_BITMASK         (0x8U)
#define PWMPER45_BIT4_BITMASK         (0x10U)
#define PWMPER45_BIT5_BITMASK         (0x20U)
#define PWMPER45_BIT6_BITMASK         (0x40U)
#define PWMPER45_BIT7_BITMASK         (0x80U)
#define PWMPER45_BIT8_BITMASK         (0x100U)
#define PWMPER45_BIT9_BITMASK         (0x200U)
#define PWMPER45_BIT10_BITMASK        (0x400U)
#define PWMPER45_BIT11_BITMASK        (0x800U)
#define PWMPER45_BIT12_BITMASK        (0x1000U)
#define PWMPER45_BIT13_BITMASK        (0x2000U)
#define PWMPER45_BIT14_BITMASK        (0x4000U)
#define PWMPER45_BIT15_BITMASK        (0x8000U)

/*** PWMPER4 - PWM Channel 4 Period Register.; 0x001B0018 ***/
#define PWMPER4                       (*((volatile uint8 *)(&__IPSBAR[0x001B0018UL])))
#define PWMPER4_PERIOD0_BITMASK       (0x1U)
#define PWMPER4_PERIOD1_BITMASK       (0x2U)
#define PWMPER4_PERIOD2_BITMASK       (0x4U)
#define PWMPER4_PERIOD3_BITMASK       (0x8U)
#define PWMPER4_PERIOD4_BITMASK       (0x10U)
#define PWMPER4_PERIOD5_BITMASK       (0x20U)
#define PWMPER4_PERIOD6_BITMASK       (0x40U)
#define PWMPER4_PERIOD7_BITMASK       (0x80U)
#define PWMPER4_PERIOD_GRPMASK        (0xFFU)
#define PWMPER4_PERIOD_GRPPOS         (0U)

/*** PWMPER5 - PWM Channel 5 Period Register.; 0x001B0019 ***/
#define PWMPER5                       (*((volatile uint8 *)(&__IPSBAR[0x001B0019UL])))
#define PWMPER5_PERIOD0_BITMASK       (0x1U)
#define PWMPER5_PERIOD1_BITMASK       (0x2U)
#define PWMPER5_PERIOD2_BITMASK       (0x4U)
#define PWMPER5_PERIOD3_BITMASK       (0x8U)
#define PWMPER5_PERIOD4_BITMASK       (0x10U)
#define PWMPER5_PERIOD5_BITMASK       (0x20U)
#define PWMPER5_PERIOD6_BITMASK       (0x40U)
#define PWMPER5_PERIOD7_BITMASK       (0x80U)
#define PWMPER5_PERIOD_GRPMASK        (0xFFU)
#define PWMPER5_PERIOD_GRPPOS         (0U)

/*** PWMPER67 - PWM Channel Period 67 Register; 0x001B001A ***/
#define PWMPER67                      (*((volatile uint16 *)(&__IPSBAR[0x001B001AUL])))
#define PWMPER67_BIT0_BITMASK         (0x1U)
#define PWMPER67_BIT1_BITMASK         (0x2U)
#define PWMPER67_BIT2_BITMASK         (0x4U)
#define PWMPER67_BIT3_BITMASK         (0x8U)
#define PWMPER67_BIT4_BITMASK         (0x10U)
#define PWMPER67_BIT5_BITMASK         (0x20U)
#define PWMPER67_BIT6_BITMASK         (0x40U)
#define PWMPER67_BIT7_BITMASK         (0x80U)
#define PWMPER67_BIT8_BITMASK         (0x100U)
#define PWMPER67_BIT9_BITMASK         (0x200U)
#define PWMPER67_BIT10_BITMASK        (0x400U)
#define PWMPER67_BIT11_BITMASK        (0x800U)
#define PWMPER67_BIT12_BITMASK        (0x1000U)
#define PWMPER67_BIT13_BITMASK        (0x2000U)
#define PWMPER67_BIT14_BITMASK        (0x4000U)
#define PWMPER67_BIT15_BITMASK        (0x8000U)

/*** PWMPER6 - PWM Channel 6 Period Register.; 0x001B001A ***/
#define PWMPER6                       (*((volatile uint8 *)(&__IPSBAR[0x001B001AUL])))
#define PWMPER6_PERIOD0_BITMASK       (0x1U)
#define PWMPER6_PERIOD1_BITMASK       (0x2U)
#define PWMPER6_PERIOD2_BITMASK       (0x4U)
#define PWMPER6_PERIOD3_BITMASK       (0x8U)
#define PWMPER6_PERIOD4_BITMASK       (0x10U)
#define PWMPER6_PERIOD5_BITMASK       (0x20U)
#define PWMPER6_PERIOD6_BITMASK       (0x40U)
#define PWMPER6_PERIOD7_BITMASK       (0x80U)
#define PWMPER6_PERIOD_GRPMASK        (0xFFU)
#define PWMPER6_PERIOD_GRPPOS         (0U)

/*** PWMPER7 - PWM Channel 7 Period Register.; 0x001B001B ***/
#define PWMPER7                       (*((volatile uint8 *)(&__IPSBAR[0x001B001BUL])))
#define PWMPER7_PERIOD0_BITMASK       (0x1U)
#define PWMPER7_PERIOD1_BITMASK       (0x2U)
#define PWMPER7_PERIOD2_BITMASK       (0x4U)
#define PWMPER7_PERIOD3_BITMASK       (0x8U)
#define PWMPER7_PERIOD4_BITMASK       (0x10U)
#define PWMPER7_PERIOD5_BITMASK       (0x20U)
#define PWMPER7_PERIOD6_BITMASK       (0x40U)
#define PWMPER7_PERIOD7_BITMASK       (0x80U)
#define PWMPER7_PERIOD_GRPMASK        (0xFFU)
#define PWMPER7_PERIOD_GRPPOS         (0U)

/*** PWMDTY0 - PWM Channel 0 Duty Register.; 0x001B001C ***/
#define PWMDTY0                       (*((volatile uint8 *)(&__IPSBAR[0x001B001CUL])))
#define PWMDTY0_DUTY0_BITMASK         (0x1U)
#define PWMDTY0_DUTY1_BITMASK         (0x2U)
#define PWMDTY0_DUTY2_BITMASK         (0x4U)
#define PWMDTY0_DUTY3_BITMASK         (0x8U)
#define PWMDTY0_DUTY4_BITMASK         (0x10U)
#define PWMDTY0_DUTY5_BITMASK         (0x20U)
#define PWMDTY0_DUTY6_BITMASK         (0x40U)
#define PWMDTY0_DUTY7_BITMASK         (0x80U)
#define PWMDTY0_DUTY_GRPMASK          (0xFFU)
#define PWMDTY0_DUTY_GRPPOS           (0U)

/*** PWMDTY01 - PWM Channel Duty 01 Register; 0x001B001C ***/
#define PWMDTY01                      (*((volatile uint16 *)(&__IPSBAR[0x001B001CUL])))
#define PWMDTY01_BIT0_BITMASK         (0x1U)
#define PWMDTY01_BIT1_BITMASK         (0x2U)
#define PWMDTY01_BIT2_BITMASK         (0x4U)
#define PWMDTY01_BIT3_BITMASK         (0x8U)
#define PWMDTY01_BIT4_BITMASK         (0x10U)
#define PWMDTY01_BIT5_BITMASK         (0x20U)
#define PWMDTY01_BIT6_BITMASK         (0x40U)
#define PWMDTY01_BIT7_BITMASK         (0x80U)
#define PWMDTY01_BIT8_BITMASK         (0x100U)
#define PWMDTY01_BIT9_BITMASK         (0x200U)
#define PWMDTY01_BIT10_BITMASK        (0x400U)
#define PWMDTY01_BIT11_BITMASK        (0x800U)
#define PWMDTY01_BIT12_BITMASK        (0x1000U)
#define PWMDTY01_BIT13_BITMASK        (0x2000U)
#define PWMDTY01_BIT14_BITMASK        (0x4000U)
#define PWMDTY01_BIT15_BITMASK        (0x8000U)

/*** PWMDTY1 - PWM Channel 1 Duty Register.; 0x001B001D ***/
#define PWMDTY1                       (*((volatile uint8 *)(&__IPSBAR[0x001B001DUL])))
#define PWMDTY1_DUTY0_BITMASK         (0x1U)
#define PWMDTY1_DUTY1_BITMASK         (0x2U)
#define PWMDTY1_DUTY2_BITMASK         (0x4U)
#define PWMDTY1_DUTY3_BITMASK         (0x8U)
#define PWMDTY1_DUTY4_BITMASK         (0x10U)
#define PWMDTY1_DUTY5_BITMASK         (0x20U)
#define PWMDTY1_DUTY6_BITMASK         (0x40U)
#define PWMDTY1_DUTY7_BITMASK         (0x80U)
#define PWMDTY1_DUTY_GRPMASK          (0xFFU)
#define PWMDTY1_DUTY_GRPPOS           (0U)

/*** PWMDTY2 - PWM Channel 2 Duty Register.; 0x001B001E ***/
#define PWMDTY2                       (*((volatile uint8 *)(&__IPSBAR[0x001B001EUL])))
#define PWMDTY2_DUTY0_BITMASK         (0x1U)
#define PWMDTY2_DUTY1_BITMASK         (0x2U)
#define PWMDTY2_DUTY2_BITMASK         (0x4U)
#define PWMDTY2_DUTY3_BITMASK         (0x8U)
#define PWMDTY2_DUTY4_BITMASK         (0x10U)
#define PWMDTY2_DUTY5_BITMASK         (0x20U)
#define PWMDTY2_DUTY6_BITMASK         (0x40U)
#define PWMDTY2_DUTY7_BITMASK         (0x80U)
#define PWMDTY2_DUTY_GRPMASK          (0xFFU)
#define PWMDTY2_DUTY_GRPPOS           (0U)

/*** PWMDTY23 - PWM Channel Duty 23 Register; 0x001B001E ***/
#define PWMDTY23                      (*((volatile uint16 *)(&__IPSBAR[0x001B001EUL])))
#define PWMDTY23_BIT0_BITMASK         (0x1U)
#define PWMDTY23_BIT1_BITMASK         (0x2U)
#define PWMDTY23_BIT2_BITMASK         (0x4U)
#define PWMDTY23_BIT3_BITMASK         (0x8U)
#define PWMDTY23_BIT4_BITMASK         (0x10U)
#define PWMDTY23_BIT5_BITMASK         (0x20U)
#define PWMDTY23_BIT6_BITMASK         (0x40U)
#define PWMDTY23_BIT7_BITMASK         (0x80U)
#define PWMDTY23_BIT8_BITMASK         (0x100U)
#define PWMDTY23_BIT9_BITMASK         (0x200U)
#define PWMDTY23_BIT10_BITMASK        (0x400U)
#define PWMDTY23_BIT11_BITMASK        (0x800U)
#define PWMDTY23_BIT12_BITMASK        (0x1000U)
#define PWMDTY23_BIT13_BITMASK        (0x2000U)
#define PWMDTY23_BIT14_BITMASK        (0x4000U)
#define PWMDTY23_BIT15_BITMASK        (0x8000U)

/*** PWMDTY3 - PWM Channel 3 Duty Register.; 0x001B001F ***/
#define PWMDTY3                       (*((volatile uint8 *)(&__IPSBAR[0x001B001FUL])))
#define PWMDTY3_DUTY0_BITMASK         (0x1U)
#define PWMDTY3_DUTY1_BITMASK         (0x2U)
#define PWMDTY3_DUTY2_BITMASK         (0x4U)
#define PWMDTY3_DUTY3_BITMASK         (0x8U)
#define PWMDTY3_DUTY4_BITMASK         (0x10U)
#define PWMDTY3_DUTY5_BITMASK         (0x20U)
#define PWMDTY3_DUTY6_BITMASK         (0x40U)
#define PWMDTY3_DUTY7_BITMASK         (0x80U)
#define PWMDTY3_DUTY_GRPMASK          (0xFFU)
#define PWMDTY3_DUTY_GRPPOS           (0U)

/*** PWMDTY4 - PWM Channel 4 Duty Register.; 0x001B0020 ***/
#define PWMDTY4                       (*((volatile uint8 *)(&__IPSBAR[0x001B0020UL])))
#define PWMDTY4_DUTY0_BITMASK         (0x1U)
#define PWMDTY4_DUTY1_BITMASK         (0x2U)
#define PWMDTY4_DUTY2_BITMASK         (0x4U)
#define PWMDTY4_DUTY3_BITMASK         (0x8U)
#define PWMDTY4_DUTY4_BITMASK         (0x10U)
#define PWMDTY4_DUTY5_BITMASK         (0x20U)
#define PWMDTY4_DUTY6_BITMASK         (0x40U)
#define PWMDTY4_DUTY7_BITMASK         (0x80U)
#define PWMDTY4_DUTY_GRPMASK          (0xFFU)
#define PWMDTY4_DUTY_GRPPOS           (0U)

/*** PWMDTY45 - PWM Channel Duty 45 Register; 0x001B0020 ***/
#define PWMDTY45                      (*((volatile uint16 *)(&__IPSBAR[0x001B0020UL])))
#define PWMDTY45_BIT0_BITMASK         (0x1U)
#define PWMDTY45_BIT1_BITMASK         (0x2U)
#define PWMDTY45_BIT2_BITMASK         (0x4U)
#define PWMDTY45_BIT3_BITMASK         (0x8U)
#define PWMDTY45_BIT4_BITMASK         (0x10U)
#define PWMDTY45_BIT5_BITMASK         (0x20U)
#define PWMDTY45_BIT6_BITMASK         (0x40U)
#define PWMDTY45_BIT7_BITMASK         (0x80U)
#define PWMDTY45_BIT8_BITMASK         (0x100U)
#define PWMDTY45_BIT9_BITMASK         (0x200U)
#define PWMDTY45_BIT10_BITMASK        (0x400U)
#define PWMDTY45_BIT11_BITMASK        (0x800U)
#define PWMDTY45_BIT12_BITMASK        (0x1000U)
#define PWMDTY45_BIT13_BITMASK        (0x2000U)
#define PWMDTY45_BIT14_BITMASK        (0x4000U)
#define PWMDTY45_BIT15_BITMASK        (0x8000U)

/*** PWMDTY5 - PWM Channel 5 Duty Register.; 0x001B0021 ***/
#define PWMDTY5                       (*((volatile uint8 *)(&__IPSBAR[0x001B0021UL])))
#define PWMDTY5_DUTY0_BITMASK         (0x1U)
#define PWMDTY5_DUTY1_BITMASK         (0x2U)
#define PWMDTY5_DUTY2_BITMASK         (0x4U)
#define PWMDTY5_DUTY3_BITMASK         (0x8U)
#define PWMDTY5_DUTY4_BITMASK         (0x10U)
#define PWMDTY5_DUTY5_BITMASK         (0x20U)
#define PWMDTY5_DUTY6_BITMASK         (0x40U)
#define PWMDTY5_DUTY7_BITMASK         (0x80U)
#define PWMDTY5_DUTY_GRPMASK          (0xFFU)
#define PWMDTY5_DUTY_GRPPOS           (0U)

/*** PWMDTY6 - PWM Channel 6 Duty Register.; 0x001B0022 ***/
#define PWMDTY6                       (*((volatile uint8 *)(&__IPSBAR[0x001B0022UL])))
#define PWMDTY6_DUTY0_BITMASK         (0x1U)
#define PWMDTY6_DUTY1_BITMASK         (0x2U)
#define PWMDTY6_DUTY2_BITMASK         (0x4U)
#define PWMDTY6_DUTY3_BITMASK         (0x8U)
#define PWMDTY6_DUTY4_BITMASK         (0x10U)
#define PWMDTY6_DUTY5_BITMASK         (0x20U)
#define PWMDTY6_DUTY6_BITMASK         (0x40U)
#define PWMDTY6_DUTY7_BITMASK         (0x80U)
#define PWMDTY6_DUTY_GRPMASK          (0xFFU)
#define PWMDTY6_DUTY_GRPPOS           (0U)

/*** PWMDTY67 - PWM Channel Duty 67 Register; 0x001B0022 ***/
#define PWMDTY67                      (*((volatile uint16 *)(&__IPSBAR[0x001B0022UL])))
#define PWMDTY67_BIT0_BITMASK         (0x1U)
#define PWMDTY67_BIT1_BITMASK         (0x2U)
#define PWMDTY67_BIT2_BITMASK         (0x4U)
#define PWMDTY67_BIT3_BITMASK         (0x8U)
#define PWMDTY67_BIT4_BITMASK         (0x10U)
#define PWMDTY67_BIT5_BITMASK         (0x20U)
#define PWMDTY67_BIT6_BITMASK         (0x40U)
#define PWMDTY67_BIT7_BITMASK         (0x80U)
#define PWMDTY67_BIT8_BITMASK         (0x100U)
#define PWMDTY67_BIT9_BITMASK         (0x200U)
#define PWMDTY67_BIT10_BITMASK        (0x400U)
#define PWMDTY67_BIT11_BITMASK        (0x800U)
#define PWMDTY67_BIT12_BITMASK        (0x1000U)
#define PWMDTY67_BIT13_BITMASK        (0x2000U)
#define PWMDTY67_BIT14_BITMASK        (0x4000U)
#define PWMDTY67_BIT15_BITMASK        (0x8000U)

/*** PWMDTY7 - PWM Channel 7 Duty Register.; 0x001B0023 ***/
#define PWMDTY7                       (*((volatile uint8 *)(&__IPSBAR[0x001B0023UL])))
#define PWMDTY7_DUTY0_BITMASK         (0x1U)
#define PWMDTY7_DUTY1_BITMASK         (0x2U)
#define PWMDTY7_DUTY2_BITMASK         (0x4U)
#define PWMDTY7_DUTY3_BITMASK         (0x8U)
#define PWMDTY7_DUTY4_BITMASK         (0x10U)
#define PWMDTY7_DUTY5_BITMASK         (0x20U)
#define PWMDTY7_DUTY6_BITMASK         (0x40U)
#define PWMDTY7_DUTY7_BITMASK         (0x80U)
#define PWMDTY7_DUTY_GRPMASK          (0xFFU)
#define PWMDTY7_DUTY_GRPPOS           (0U)


#endif /* __MCF52259_PWM_H__ */
